Atmel AT85DVK-07 Specifications

1 7632A–MP3–03/06Features• Audio Processor– Proprietary Digital Signal Processor– MP3 (Full MPEG I/II-Layer 3) Decoder (1)– Windows Media® Audio (WMA

10AT85C51SND3Bx 7632A–MP3–03/06USB Controller Table 7. USB Controller Signal DescriptionNFCLE OCommand Latch Enable SignalAsserted high during comma

100AT85C51SND3Bx 7632A–MP3–03/06USB Software Operating modesDepending on the USB operating mode, the software should perform some of the follow-ing o

101 AT85C51SND3Bx7632A–MP3–03/06USB Device Operating modesIntroduction The USB device controller supports high speed and full speed data transfers. I

102AT85C51SND3Bx 7632A–MP3–03/06At the end of the reset process (Full or High), the end of reset interrupt (EORSTI) is gen-erated. Then the CPU shoul

103 AT85C51SND3Bx7632A–MP3–03/06– Clear DFCRDY to freeze the DFC transfer,– If the CPU EPNUM has to be changed: EPNUMS cleared, EPNUM = endpoint0– Re

104AT85C51SND3Bx 7632A–MP3–03/06• the host sends a SETUP command (SET_ADDRESS(addr)),• the firmware records that address in UADD, but keep ADDEN clea

105 AT85C51SND3Bx7632A–MP3–03/06Figure 61. Detach a device in Full-speed:Remote Wake-Up The “Remote Wake-up” (or “upstream resume”) request is the o

106AT85C51SND3Bx 7632A–MP3–03/06This function is compliant with the Chapter 8 test from PMTC that send extra status for a GET_DESCRIPTOR. The firmwar

107 AT85C51SND3Bx7632A–MP3–03/06Control Read The next figure shows a control read transaction. The USB controller has to manage the simultaneous writ

108AT85C51SND3Bx 7632A–MP3–03/06banks, clearing the FIFOCON bit will switch to the next bank. The RXOUTI and FIFO-CON bits are then updated by hardwa

109 AT85C51SND3Bx7632A–MP3–03/06• The CPU can read the data from the current bank (“N” read of UEDATX),• The CPU can free the bank by clearing FIFOCO

11 AT85C51SND3Bx7632A–MP3–03/06Audio Processor Table 8. I2S Output DescriptionTable 9. Audio Codec DescriptionUID IUSB OTG Identifier InputThis pin

110AT85C51SND3Bx 7632A–MP3–03/06writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is c

111 AT85C51SND3Bx7632A–MP3–03/06• The CPU can free the bank by clearing FIFOCON when all the data are written, that is:– after “N” write into UEDATX–

112AT85C51SND3Bx 7632A–MP3–03/06Table 111. Abort flowIsochronous Mode For Isochronous IN endpoints, it is possible to automatically switch the banks

113 AT85C51SND3Bx7632A–MP3–03/06Interrupts Figure 62 shows all the device interrupts sources while Figure 63 details the endpoint interrupt sources.F

114AT85C51SND3Bx 7632A–MP3–03/06Figure 63. USB Device Controller Endpoint Interrupt SystemProcessing interrupts are generated when the following eve

115 AT85C51SND3Bx7632A–MP3–03/06RegistersUSB Device General RegistersReset Value = 0000 0001bTable 112. UDCON RegisterUDCON (1.D9h) – USB Device Gen

116AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000b3 EORSTIEnd Of Reset Interrupt FlagSet by hardware when an “End Of Reset” has been detected b

117 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000b0 SUSPESuspend Interrupt Enable BitSet to ena

118AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bUSB Device Endpoint RegistersReset Value = 0000 0000bBitNumberBitMnem

119 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bBit NumberBit MnemonicDescription7 -ReservedThe value read from these

12AT85C51SND3Bx 7632A–MP3–03/06Parallel Slave Interface Table 10. PSI Signal DescriptionSerial Interfaces Table 11. SPI Controller Signal Descripti

120AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 122. UECFG0X RegisterUECFG0X (1.CCh) – USB Endpoint Configuration 1 Register7 6 5 4 3

121 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000b3-2 EPBK1:0Endpoint Bank BitsSet this field according to the endpoint size: 00b: Single bank

122AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000b1-0NBUSYBK1:0Busy Bank FlagSet by hardware to indicate the number of

123 AT85C51SND3Bx7632A–MP3–03/06Table 126. UEINTX Register (bit addressable)UEINTX (1.C8h) – USB Endpoint Interrupt Register7 6 5 4 3 2 1 0FIFOCON N

124AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000b1 STALLIStall Interrupt FlagSet by hardware to signal that a STALL ha

125 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bTable 128. UEDATX RegisterUEDATX (1.D3h) – U

126AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000b.Table 131. UEINT RegisterUEINT (1.D6h) – USB Endpoint Interrupt Register7 6 5 4 3 2 1 0- EP

127 AT85C51SND3Bx7632A–MP3–03/06USB Host Operating ModesPipe Description For the USB Host controller, the term of Pipe is used instead of Endpoint fo

128AT85C51SND3Bx 7632A–MP3–03/06The Host controller enters in Suspend state when the USB bus is in Suspend state, i.e. when the Host controller doesn

129 AT85C51SND3Bx7632A–MP3–03/06Pipe Configuration The following flow must be respected in order to activate a Pipe:Figure 66. Pipe activation flow:

13 AT85C51SND3Bx7632A–MP3–03/06MMI Interface Table 13. Keypad Controller Signal DescriptionTable 14. LCD Interface Signal DescriptionPower Manageme

130AT85C51SND3Bx 7632A–MP3–03/06USB Reset The USB controller sends a USB Reset when the firmware set the RESET bit. The RSTI bit is set by hardware w

131 AT85C51SND3Bx7632A–MP3–03/06The firmware has to change the Token for each phase.The initial data toggle is set for the corresponding token (ONLY

132AT85C51SND3Bx 7632A–MP3–03/06“Manual” Mode The TXOUT bit is set by hardware when the current bank becomes free. This triggers an interrupt if the

133 AT85C51SND3Bx7632A–MP3–03/06“Autoswitch” Mode In this mode, the clear of the FIFOCON bit is performed automatically by hardware each time the Pip

134AT85C51SND3Bx 7632A–MP3–03/06“Autoswitch” Mode In this mode, the clear of the FIFOCON bit is performed automatically by hardware each time the Pip

135 AT85C51SND3Bx7632A–MP3–03/06Figure 68. USB Host Controller Pipe Interrupt SystemFLERREUPIENX.7TXOUTIUPINTX.2TXOUTEUPIENX.2TXSTPIUPINTX.3TXSTPEUP

136AT85C51SND3Bx 7632A–MP3–03/06RegistersGeneral USB Host RegistersReset Value = 0000 0000bTable 132. UHCON RegisterUHCON (1.D9h) – USB Host Genera

137 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000b4 RXRSMIUpstream Resume Received InterruptSet by hardware when an Upstream Resume has been re

138AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000b0 DCONNEDevice Connection Interrupt EnableSet

139 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bUSB Host Pipe RegistersReset Value = 0000 0000bTable 137. UHFNUML R

14AT85C51SND3Bx 7632A–MP3–03/06OCD Interface Table 16. OCD Signal DescriptionBVSS GNDBattery GroundConnect this pin to the negative pin of the batte

140AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 140. UPRST RegisterUPRST (1.CAh) – USB Host Pipe Reset Register7 6 5 4 3 2 1 0- P6RST

141 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000b5 INMODEIN Request modeSet this bit to allow the USB controller to pe

142AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 143. UPCFG1X RegisterUPCFG1X (1.CDh) – USB Pipe Configuration

143 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bTable 145. UPSTAX RegisterUPSTAX (1.CEh) – USB Pipe Status Register7 6 5 4 3 2 1 0CFGOK OVER

144AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 146. UPINRQX RegisterUPINRQX (1.DFh) – USB Pipe IN Number Of R

145 AT85C51SND3Bx7632A–MP3–03/06Table 148. UPINTX RegisterUPINTX (1.C8h) – USB Pipe Interrupt Register7 6 5 4 3 2 1 0FIFOCON NAKEDI RWAL PERRI TXSTP

146AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000b0 RXINIIN Data receivedSet by hardware when a new USB message is stor

147 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bBit NumberBit MnemonicDescription7-0 PDAT7:0P

148AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 153. UPINT RegisterUPINT (1.D6h) – USB Pipe IN Number Of Request Register7 6 5 4 3 2 1

149 AT85C51SND3Bx7632A–MP3–03/06Audio Controller The Audio Controller embedded in AT85C51SND3Bx is based on four functional blocks detailed in the fo

15 AT85C51SND3Bx7632A–MP3–03/06Internal Pin Structure Table 17. Detailed Internal Pin StructureCircuit(1)Type PinsInput/Output RSTInput/OutputP0.7:0

150AT85C51SND3Bx 7632A–MP3–03/06Figure 71. Audio Processor Block DiagramAudio Buffer The audio buffer receives the audio data flow coming from DFC o

151 AT85C51SND3Bx7632A–MP3–03/06In order to avoid any spurious interrupts on the CPU side when a data transfer with the data flow controller is estab

152AT85C51SND3Bx 7632A–MP3–03/06Digital Volume Control The digital volume is controlled separately on right and left channel by setting the DVR4:0 an

153 AT85C51SND3Bx7632A–MP3–03/06Mixing Mode A mixing mode can be established by setting MIXEN bit in AUCON. It consists in mixing the ADC output comi

154AT85C51SND3Bx 7632A–MP3–03/06Audio Codec The audio codec is controlled by four registers as detailed in Figure 74: Figure 74. Audio Codec Block D

155 AT85C51SND3Bx7632A–MP3–03/06Table 157. Audio Codec Output GainOutput Drive Control Output buffers can operate in two modes depending on the powe

156AT85C51SND3Bx 7632A–MP3–03/06Line Inputs Preamplifier Gain In AT85C51SND3B2 & AT85C51SND3B3, when Line Inputs are selected as output source (e

157 AT85C51SND3Bx7632A–MP3–03/06Figure 75. Audio DAC Interface Block DiagramClock Controller As soon as audio DAC interface is enabled by setting AD

158AT85C51SND3Bx 7632A–MP3–03/06Figure 77. Audio Output FormatRegistersDSELDCLKDDATMSBI2S Format with DSIZE = 0 and JUST4:0 = 00001.LSB B14 MSBLSB B

159 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000b2-1 -ReservedThe value read from these bits is always 0. Do not set t

16AT85C51SND3Bx 7632A–MP3–03/06OutputSDCLKSCKNFCE3:0NFCLENFALENFWENFRENFWPSMCEDSELDDATDCLKOCLKLWR/LELA0/LRSLRD/LRWLCSUVCONTXDInput/OutputDPFDMFInput/

160AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000b1 APLOADAudio Processor Load Enable BitSet to

161 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bTable 170. APIEN RegisterAPIEN (1.E9h) – Aud

162AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 173. APTIM2 RegisterAPTIM2 (2.C9h) – Audio Processor Timer Reg

163 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bTable 176. APELEV Register APELEV (2.F7h) - Audio Processor Equalizer Level Status Register7

164AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000b0AOEN-AT85C51SND3B2 and AT85C51SND3B3: Audio

165 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 180. ACOLG Register (AT85C51SND3B2 and AT85C51SND3B3 only)ACOL

166AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 1000bReset Value = 0000 0000bReset Value = 0000 0000b1-2 OVERS1:0Audio Ove

167 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 186. ASSTA1 RegisterASSTA1 (2.E3h) – Audio Stream Status Regis

168AT85C51SND3Bx 7632A–MP3–03/06Nand Flash ControllerThe AT85C51SND3Bx implement a hardware Nand Flash Controller (NFC) embedding the following featu

169 AT85C51SND3Bx7632A–MP3–03/06Figure 79. Nand Flash ConnectionClock Unit The NFC clock is generated based on the clock generator as detailed in Se

17 AT85C51SND3Bx7632A–MP3–03/06Notes: 1. For information on resistor value, input/output levels, and drive capability, refer to Section “DC Character

170AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0001 1110bTable 189. NFPGCFG / SMPGCFG RegistersNFPGCFG / SMPGCFG – NF / SMC D

171 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bSpecific Action As soon as the NFC is configured, the NFC is ‘idle’, i.e. ready for operation

172AT85C51SND3Bx 7632A–MP3–03/06Table 193. Device Selection Allowed Configuration“Read” Session A “read” session is launched and the DFC flow contro

173 AT85C51SND3Bx7632A–MP3–03/06Note that it is not possible to reset A9:8 after each command (write in NFCMD): the device status read command is use

174AT85C51SND3Bx 7632A–MP3–03/06Data Reading/Writing The NFDAT and NFDATF registers allow reading or writing of a byte without the use of the DFC as

175 AT85C51SND3Bx7632A–MP3–03/06Assembly code: mov #, direct• A read of NFDAT returns to the CPU the byte contained in that register, but does not la

176AT85C51SND3Bx 7632A–MP3–03/06Figure 80. Nand Flash Read ExampleLegend:•“ifc CPU” illustrates the commands given by the CPU to the NFC.• “auto” il

177 AT85C51SND3Bx7632A–MP3–03/06Table 195. Spare Zone ContentThe bytes which are not managed by the NFC are written to FFh.Write Session The spare z

178AT85C51SND3Bx 7632A–MP3–03/06Spare Zone Mode 1 The spare zone is not managed by the NFC. The data zone is contiguous.The user sends the commands t

179 AT85C51SND3Bx7632A–MP3–03/06• read the ECC FIFO, (keeping the ECCs in memory), re-initialize it, resume the data transfer, and to write all the E

18AT85C51SND3Bx 7632A–MP3–03/06Power Management The Power Management implements all the internal power circuitry (regulators, links…) as well as powe

180AT85C51SND3Bx 7632A–MP3–03/06Write Protection The NFC provides a hardware mechanism to protect full or part of the memory against any spurious wri

181 AT85C51SND3Bx7632A–MP3–03/06Figure 81. Nand Flash Write Protection SchemeSince the NFWP signal state is part of the device status, the user can

182AT85C51SND3Bx 7632A–MP3–03/06Card UnitEnable Smartmedia or XD card management is enabled by setting SMCEN bit in SCFG1 regis-ter as detailed in Se

183 AT85C51SND3Bx7632A–MP3–03/06Card Lock Input As shown in Figure 83 the SMLCK (SMC/XD Lock) input implements an internal pull-up, in order to provi

184AT85C51SND3Bx 7632A–MP3–03/06• or illegal operation (ILGLI)– Attempt to access a NF device which is not declared (e.g. DEV= 4 while NUMDEV= 2)– Wr

185 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 204. NFCON RegisterNFCON (1.9Bh) – Nand Flash Controller Contr

186AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bA read of that register returns an unexpected value.Reset Value = 0000 0000bReset Value = 000

187 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 210. NFDAT RegisterNFDAT (1.A2h) – Nand-Flash Controller Data

188AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000b0 NFRUNRunning FlagSet by hardware to signal

189 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 215. NFIEN RegisterNFIEN (1.A6h) – Nand Flash Controller Inter

19 AT85C51SND3Bx7632A–MP3–03/06Schematic Figure 6. Regulator ConnectionNote: Depending on power supply scheme, CLV may replace CDC capacitor (see Fi

190AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 217. NFBPH RegisterNFUDAT (1.94h) – Nand Flash Controller Byte

191 AT85C51SND3Bx7632A–MP3–03/06MMC/SD Controller The AT85C51SND3Bx embed a MMC/SD controller allowing connecting of MMC and SD cards in 1-bit or 4-b

192AT85C51SND3Bx 7632A–MP3–03/06tion from the card through the SDCMD line. These channels are detailed in the following sections.Figure 87. Command

193 AT85C51SND3Bx7632A–MP3–03/06Figure 88. Command Transmission FlowCommand Receiver The end of the response reception is signalled by the EORI flag

194AT85C51SND3Bx 7632A–MP3–03/06Data Line Controller As shown in Figure 89, the data line controller is based on a 16-Byte FIFO used both by the data

195 AT85C51SND3Bx7632A–MP3–03/06Data Configuration Before sending or receiving any data, the data line controller must be configured accord-ing to th

196AT85C51SND3Bx 7632A–MP3–03/06Data Transmission Transmission is enabled by setting DATEN bit in MMCON1 register. FIFO must be filled after this fla

197 AT85C51SND3Bx7632A–MP3–03/06Figure 91. Data Stream Transmission FlowsSendSTOP CommandData Stream TransmissionFIFO Fillingwrite 16 data to MMDATF

198AT85C51SND3Bx 7632A–MP3–03/06Figure 92. Data Block Transmission FlowsData ReceiverConfiguration To receive data from the card the data controller

199 AT85C51SND3Bx7632A–MP3–03/06from such situation. In case of time-out, the data controller and its internal state machine may be reset by setting

2AT85C51SND3Bx 7632A–MP3–03/06• Packages– LQFP100, BGA100, DiceNotes: 1. See Ordering Information2. Future product3. AT85C51SND3B2 & AT85C51SND3B

20AT85C51SND3Bx 7632A–MP3–03/06Battery Voltage Monitor The battery voltage monitor is a 5-bit / 50 mV resolution A to D converter with fixed con-vers

200AT85C51SND3Bx 7632A–MP3–03/06Figure 94. Data Block Reception FlowsCard ManagementCard Detect Input As shown in Figure 95 the SDINS (MMC/SD Card D

201 AT85C51SND3Bx7632A–MP3–03/06Figure 96. SD Card Write Protection Input Block DiagramInterrupt As shown in Figure 97, the MMC controller implement

202AT85C51SND3Bx 7632A–MP3–03/06RegistersReset Value = 0000 0010bTable 221. MMCON0 RegisterMMCON0 (1.B1h) – MMC Control Register 07 6 5 4 3 2 1 0- D

203 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000b2 DATENData Transfer Enable BitSet to enable data transmission or rec

204AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = XX00 0000b, depends wether a card is present in the socket or not and if it is

205 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bTable 226. MMINT RegisterMMINT (1.BEh Read Only) – MMC Interrupt Register7 6 5 4 3 2 1 0CDET

206AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 1111 1110bReset Value = 1111 1111bReset Value = 1111 1111b6 EORMEnd Of Response Interrupt Mask BitSet t

207 AT85C51SND3Bx7632A–MP3–03/06Parallel Slave InterfaceThe AT85C51SND3Bx implement a Parallel Slave Interface (PSI) allowing parallel con-nection wi

208AT85C51SND3Bx 7632A–MP3–03/06PSI Addressing The AT85C51SND3Bx are accessible by a host in read or write at two different address locations by sett

209 AT85C51SND3Bx7632A–MP3–03/06Figure 102. Write Data Sampling Configuration“SA0= H” Mode The “SA0= H” mode is particularly fitting control managem

21 AT85C51SND3Bx7632A–MP3–03/06Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halt

210AT85C51SND3Bx 7632A–MP3–03/06Host can then read or write by burst an amount of data defined by the protocol (see Section “Data Flow Controller”, p

211 AT85C51SND3Bx7632A–MP3–03/06RegistersReset Value = 0000 0000bTable 231. PSICON RegisterPSICON (1.ADh) – PSI Control Register 7 6 5 4 3 2 1 0PSEN

212AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 1000 0000bReset Value = 0000 0000bReset Value = 0000 0000b3-0 -ReservedThe value read from these bits i

213 AT85C51SND3Bx7632A–MP3–03/06Serial I/O PortThe AT85C51SND3Bx implement a Serial Input/Output Port (SIO) allowing serial com-munication. By using

214AT85C51SND3Bx 7632A–MP3–03/06Figure 106. SIO Block DiagramCharacter Format The character consists of five fields: start, data, parity, stop and g

215 AT85C51SND3Bx7632A–MP3–03/06Table 238. Stop Bit Number SelectionGuard Field The guard field is not part of a character and is an optional inter-

216AT85C51SND3Bx 7632A–MP3–03/06Figure 109. Baud Rate Generator Block DiagramTable 240. Baud Rate Generator Value (12x oversampling)Note: 1. This h

217 AT85C51SND3Bx7632A–MP3–03/06Receiver As shown in Figure 110, the receiver is based on a character handler taking care of character integrity chec

218AT85C51SND3Bx 7632A–MP3–03/06Receiver Errors There are three kinds of errors that can be set during character reception: the framing error, the pa

219 AT85C51SND3Bx7632A–MP3–03/06Figure 113. SIO Controller Interrupt SystemRegistersReset Value = 0000 0000bPEIESIEN.3TIESIEN.1SIOInterruptRISINT.0F

22AT85C51SND3Bx 7632A–MP3–03/06the clocks to the CPU and peripherals. Using INTn input, execution resumes when the input is released (see Figure 10)

220AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 243. SFCON RegisterSFCON (0.95h) – SIO Flow Control Register7 6 5 4 3 2 1 0OVRSF3 OVRS

221 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0X10 0010bReset Value = 0000 0000b1 TITransmission Interrupt FlagSet by hardware when the Tx FIFO is no

222AT85C51SND3Bx 7632A–MP3–03/06Reset Value = XXXX XXXXbReset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bTable 246. SBUF Regi

223 AT85C51SND3Bx7632A–MP3–03/06Serial Peripheral InterfaceThe AT85C51SND3Bx implement a Synchronous Peripheral Interface (SPI) allowing full-duplex,

224AT85C51SND3Bx 7632A–MP3–03/06Figure 115. Typical Slave SPI Bus ConfigurationDescription The SPI controller interfaces with the C51 core through t

225 AT85C51SND3Bx7632A–MP3–03/06The transmission begins by writing to SPDAT through CPU or DFC. Writing to SPDAT writes to an intermediate register w

226AT85C51SND3Bx 7632A–MP3–03/06When the AT85C51SND3Bx is the only slave on the bus, it can be useful not to use SSpin and get it back to I/O functio

227 AT85C51SND3Bx7632A–MP3–03/06Data Transfer The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state(1) while the Cl

228AT85C51SND3Bx 7632A–MP3–03/06Figure 120 shows a SPI transmission with CPHA = 1, where the first SCK edge is used by the slave as a start of transm

229 AT85C51SND3Bx7632A–MP3–03/06– the MSTR bit in SPCON is clearedClearing the MODF bit is accomplished by reading SPSCR with MODF bit set, followed

23 AT85C51SND3Bx7632A–MP3–03/06Reset In order to secure the product functionality while in power-up or power-down phase or while in running phase, a

230AT85C51SND3Bx 7632A–MP3–03/06OverRun Condition This error means that the speed is not adapted for the running application. An OverRun condition oc

231 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0001 0100b4 MSTRMaster Mode SelectSet to select the master mode. Clear to select the slave mode.3 CPOLS

232AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 1000bReset Value = XXXX XXXXb1 SPTEIESPTE Interrupt Enable BitSet to enable SPTE interrupt generat

233 AT85C51SND3Bx7632A–MP3–03/06Display Interface The AT85C51SND3Bx implement a display interface allowing glueless direct interfacing (thanks to its

234AT85C51SND3Bx 7632A–MP3–03/06Access Cycles The AT85C51SND3Bx enables connection of LCD controller with normalized 6800 and 8080 interface as shown

235 AT85C51SND3Bx7632A–MP3–03/06Sleep Wait Time The sleep wait time is the time between two consecutive access cycle. It can be pro-grammed by SLW1:0

236AT85C51SND3Bx 7632A–MP3–03/06RegistersReset Value= 0000 0000bTable 255. LCDCON0 RegisterLCDCON0 (1.96h) – LCD Control Register 07 6 5 4 3 2 1 0BU

237 AT85C51SND3Bx7632A–MP3–03/06Reset Value= 0000 0000bReset Value= 0000 0000bReset Value= 0000 0000b3 LCYCTCycle Type SelectionSet to select non nor

238AT85C51SND3Bx 7632A–MP3–03/06Reset Value= 0000 0000bTable 259. LCDDAT RegisterLCDDAT (1.97h) – LCD Data Register7 6 5 4 3 2 1 0LD7 LD6 LD5 LD4 LD

239 AT85C51SND3Bx7632A–MP3–03/06Keyboard Interface The AT85C51SND3Bx implement a keyboard interface allowing the connection of a 4 x n matrix keyboar

24AT85C51SND3Bx 7632A–MP3–03/06Figure 13. Reset Circuitry and Power-On ResetCold Reset 2 conditions are required before enabling a CPU start-up:•VDD

240AT85C51SND3Bx 7632A–MP3–03/06Registers Table 260. KBCON RegisterKBCON (0.A3h) – Keyboard Control RegisterReset Value = 0000 1111bTable 261. KBST

4AT85C51SND3Bx 7632A–MP3–03/06Electrical CharacteristicsAbsolute Maximum RatingDC CharacteristicsDigital Logic Table 257. Digital DC Characteristics

5 AT85C51SND3Bx7632A–MP3–03/06Oscillator & CrystalSchematic Figure 134. Crystal ConnectionNote: For operation with most standard crystals, no ex

6AT85C51SND3Bx 7632A–MP3–03/06Parameters Table 259. DC-DC Filter CharacteristicsTA = -40 to +85°CTable 260. DC-DC Power CharacteristicsVBAT = 0.9 t

7 AT85C51SND3Bx7632A–MP3–03/06Table 263. Low Voltage Regulator Power CharacteristicsHVDD = 3 to 3.6 V; TA = -40 to +85°CUSBSchematic Figure 137. US

8AT85C51SND3Bx 7632A–MP3–03/06Parameters Table 265. Audio Codec Components CharacteristicsTA = -40 to +85°CNotes: 1. Value in low impedance mode (He

9 AT85C51SND3Bx7632A–MP3–03/06AC CharacteristicsNFC InterfaceDefinition of Symbols Table 1. NFC Interface Timing Symbol DefinitionsTimings Table 267

10AT85C51SND3Bx 7632A–MP3–03/06WaveformsFigure 140. NFC Command Latch Cycle WaveformsFigure 141. NFC Address Latch Cycle WaveformsFigure 142. NFC

11 AT85C51SND3Bx7632A–MP3–03/06Figure 143. NFC Write Cycle WaveformsMMC InterfaceDefinition of symbols Table 268. MMC Interface Timing Symbol Defin

12AT85C51SND3Bx 7632A–MP3–03/06Waveforms Figure 144. MMC Input-Output WaveformsLCD Interface To be definedDefinition of SymbolsTimingsWaveformsSIO I

25 AT85C51SND3Bx7632A–MP3–03/06RegistersReset Value = 00011 0000bTable 20. PCON RegisterPCON (0.87h) – Power Control Register7 6 5 4 3 2 1 0VBCEN VB

13 AT85C51SND3Bx7632A–MP3–03/06Table 271. SPI Interface Master AC TimingVDD = 1.65 to 3.6 V; TA = -40 to +85°CNote: 1. Value of this parameter depen

14AT85C51SND3Bx 7632A–MP3–03/06Waveforms Figure 145. SPI Slave Waveforms (SSCPHA= 0)Note: 1. Not Defined but generally the MSB of the character whic

15 AT85C51SND3Bx7632A–MP3–03/06Figure 147. SPI Master Waveforms (SSCPHA= 0)Note: SS handled by software using general purpose port pin.Figure 148.

16AT85C51SND3Bx 7632A–MP3–03/06Audio DAC InterfaceDefinition of symbols Table 272. Audio DAC Interface Timing Symbol DefinitionsTimings Table 273.

17 AT85C51SND3Bx7632A–MP3–03/06Timings Table 275. External Clock AC TimingsVDD = 1.65 to 3.6 V; TA = -40 to +85°CWaveforms Figure 150. External Clo

253 AT85C51SND3Bx7632A–MP3–03/06Ordering InformationTable 280. Ordering InformationNotes: 1. Codec option, see Table 281 below.2. Contact sales offi

254AT85C51SND3Bx 7632A–MP3–03/06Package InformationLQFP 100

255 AT85C51SND3Bx7632A–MP3–03/06CTBGA 100

17632A–MP3–03/06AT85C51SND3A Table of ContentsFeatures ...

27632A–MP3–03/06AT85C51SND3A Registers...5

26AT85C51SND3Bx 7632A–MP3–03/06Reset Value = XX00 0XXXb(1)Note: 1. Reset value depends on the power supply presence and on the internal reset source.

37632A–MP3–03/06 AT85C51SND3APower-On and Reset ... 101Speed Ide

47632A–MP3–03/06AT85C51SND3A Clock Unit ... 169

57632A–MP3–03/06 AT85C51SND3AAC Characteristics...246Orderi

Printed on recycled paper.7632A–MP3–03/06© Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, are registered tradema

27 AT85C51SND3Bx7632A–MP3–03/06Clock Controller The AT85C51SND3Bx clock controller is based on an on-chip oscillator feeding two on-chip Phase Lock L

28AT85C51SND3Bx 7632A–MP3–03/06Figure 16. Crystal ConnectionClock Generator The clock generator provides the oscillator and higher frequency clocks

29 AT85C51SND3Bx7632A–MP3–03/06Figure 18. PLL Block Diagram and SymbolTable 24. PLL Reverse Clock SelectionPLL Programming The PLL is programmed de

3 AT85C51SND3Bx7632A–MP3–03/06Block DiagramFigure 1. AT85C51SND3Bx Block DiagramNotes: 1. AT85C51SND3B3 only2. AT85C51SND3B2 & AT85C51SND3B3 onl

30AT85C51SND3Bx 7632A–MP3–03/06Figure 19. System Clock Generator Block Diagram and SymbolsTable 26. System Clock SelectionX2 Feature Unlike standar

31 AT85C51SND3Bx7632A–MP3–03/06Figure 21. DFC/NFC Clock Generator Block Diagram and SymbolTable 27. DFC/NFC Clock SelectionMMC Clock Generator The

32AT85C51SND3Bx 7632A–MP3–03/06Table 28. MMC Clock SelectionTable 29. MMC Clock DividerSIO Clock Generator As detailed in Figure 23, the SIO clock

33 AT85C51SND3Bx7632A–MP3–03/06RegistersReset Value = 0000 0000bTable 31. CKCON RegisterCKCON (0.8Fh) – Clock Control Register7 6 5 4 3 2 1 0- WDX2

34AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 32. CKEN RegisterCKEN (0.B9h) – Clock Enable Register7 6 5 4 3 2 1 0CKGENE PLLEN - PLOC

35 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bTable 33. CKSEL RegisterCKSEL (0.BAh) – Clock

36AT85C51SND3Bx 7632A–MP3–03/06Special Function RegistersSFR Pagination The AT85C51SND3Bx implement a SFR pagination mechanism which allows mapping o

37 AT85C51SND3Bx7632A–MP3–03/06SFR Registers The Special Function Registers (SFRs) of the AT85C51SND3Bx fall into the categories detailed in Table 39

38AT85C51SND3Bx 7632A–MP3–03/06Table 42. Interrupt SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0IEN0 0.A8h Interrupt Enable Control 0 EA EAUP EDFC ES ET1 E

39 AT85C51SND3Bx7632A–MP3–03/06Table 46. Memory Management SFRsMnemonic Add Name 7 6 5 4 3 2 1 0MEMCBAX 0.F2h Memory CODE Base Address CBAX16:9MEMDB

4AT85C51SND3Bx 7632A–MP3–03/06Application InformationThe AT85C51SND3Bx allow design of 2 typical applications which differentiate by the power supply

40AT85C51SND3Bx 7632A–MP3–03/06USB Device Registers (HOST cleared)UDCON 1.D9h Device Global Control - - - - - - RMWKUP DETACHUDINT 1.D8hDevice Global

41 AT85C51SND3Bx7632A–MP3–03/06USB Pipe Registers (HOST set)UPNUM 1.C9h USB Host Pipe Number - - - - - PNUM2:0UPRST 1.CAh USB Host Pipe Reset - PRST6

42AT85C51SND3Bx 7632A–MP3–03/06NFBPH 1.94h NF Byte Position (MSB) BP15:8NFBPL 1.95h NF Byte Position (LSB) BP7:0Table 50. NFC SFRsMnemonicAddName 7

43 AT85C51SND3Bx7632A–MP3–03/06Note: Available in AT85C51SND3B2 & AT85C51SND3B3 only.APEBS 2.F6hAudio Processor Equalizer Band Select- - - - 0 EQ

44AT85C51SND3Bx 7632A–MP3–03/06SINT 1.A8h SIO Interrupt - - EOTI OEI PEI FEI TI RISIEN 1.A9h SIO Interrupt Enable - - EOTIE OEIE PEIE FEIE TIE RIESBU

45 AT85C51SND3Bx7632A–MP3–03/06Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.Table 59. SFR Page

46AT85C51SND3Bx 7632A–MP3–03/06Note: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.Table 60. SFR Page 1

47 AT85C51SND3Bx7632A–MP3–03/06Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.2. Available in AT85

48AT85C51SND3Bx 7632A–MP3–03/06Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.2. SVERS reset value

49 AT85C51SND3Bx7632A–MP3–03/06Memory Space The AT85C51SND3Bx provide an “all in one” 64K bytes of RAM split between the three standard C51 memory se

5 AT85C51SND3Bx7632A–MP3–03/06Low Voltage 3V SystemFigure 3. Typical Low Voltage 3V Application3V NF MemoriesSD/MMC3V DC-DCBatteryFM ModuleAT85C51SN

50AT85C51SND3Bx 7632A–MP3–03/06Table 63. Register Bank SelectionThe next 16 Bytes above the register banks form a block of bit-addressable memory sp

51 AT85C51SND3Bx7632A–MP3–03/06The Figure 27 shows the memory segments configuration after bootstrap execution along with an example of user memory s

52AT85C51SND3Bx 7632A–MP3–03/06Reset Value MEMCBA0 = 0 0000 000bReset Value MEMDBAX = 0 1111 111bReset Value MEMXBAX = 0 1111 000bTable 65. MEMCBAX

53 AT85C51SND3Bx7632A–MP3–03/06Reset Value MEMCSX = 1110 1111bReset Value MEMXSX = 0000 1110bBit NumberBit MnemonicDescription7-0 CSX7:0CODE Size Bit

54AT85C51SND3Bx 7632A–MP3–03/06

55 AT85C51SND3Bx7632A–MP3–03/06Interrupt System The AT85C51SND3Bx, like other control-oriented computer architectures, employ a program interrupt met

56AT85C51SND3Bx 7632A–MP3–03/06Table 71. Priority Within Same LevelInterrupt Name Priority NumberInterrupt Address VectorsInterrupt Request Flag Cle

57 AT85C51SND3Bx7632A–MP3–03/06Figure 28. Interrupt Control SystemEPSIIEN1.2EKBIEN1.1EMMCIEN1.5ESPIIEN1.3EX0IEN0.000011011EAIEN0.7EX1IEN0.2ET0IEN0.1

58AT85C51SND3Bx 7632A–MP3–03/06External InterruptsINT1:0 Inputs External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to b

59 AT85C51SND3Bx7632A–MP3–03/06RegistersReset Value = 0000 0000bTable 72. IEN0 RegisterIEN0 (0.A8h) – Interrupt Enable Register 07 6 5 4 3 2 1 0EA E

6AT85C51SND3Bx 7632A–MP3–03/06Pin DescriptionPinoutsFigure 4. AT85C51SND3Bx 100-pin QFP PackageNotes: 1. Leave these pins unconnected for AT85C51SND

60AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 73. IEN1 RegisterIEN1 (0.B1h) – Interrupt Enable Register 176543210- - EMMC ENFC ESPI E

61 AT85C51SND3Bx7632A–MP3–03/06Reset Value = X000 0000bTable 74. IPH0 RegisterIPH0 (0.B7h) – Interrupt Priority High Register 07 6 5 4 3 2 1 0- IPHA

62AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 75. IPH1 Register IPH1 (0.B3h) – Interrupt Priority High Register 17 6 5 4 3 2 1 0- - I

63 AT85C51SND3Bx7632A–MP3–03/06Reset Value = X000 0000bTable 76. IPL0 RegisterIPL0 (0.B8h) - Interrupt Priority Low Register 07 6 5 4 3 2 1 0- IPLAU

64AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 77. IPL1 RegisterIPL1 (0.B2h) – Interrupt Priority Low Register 17 6 5 4 3 2 1 0- - IPL

65 AT85C51SND3Bx7632A–MP3–03/06Timers/Counters The AT85C51SND3Bx implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0

66AT85C51SND3Bx 7632A–MP3–03/06Figure 31. Timer 0 and Timer 1 Clock Controller and SymbolsTimer 0 Timer 0 functions as either a Timer or event Count

67 AT85C51SND3Bx7632A–MP3–03/06Figure 32. Timer/Counter x (x = 0 or 1) in Mode 0Figure 33. Mode 0 Overflow Period FormulaMode 1 (16-bit Timer) Mode

68AT85C51SND3Bx 7632A–MP3–03/06Figure 36. Timer/Counter x (x = 0 or 1) in Mode 2Figure 37. Mode 2 Auto-reload Period FormulaMode 3 (2 x 8-bit Timer

69 AT85C51SND3Bx7632A–MP3–03/06Timer 0 Enhanced Mode Timer 0 overflow period can be increased in all modes by enabling a divider as detailed in Figur

7 AT85C51SND3Bx7632A–MP3–03/06Signals DescriptionSystem Table 1. System Signal DescriptionTable 2. Ports Signal DescriptionSignal NameType Descript

70AT85C51SND3Bx 7632A–MP3–03/06• It is important to stop the Timer/Counter before changing modes.Table 80. Timer/counter 1 Operating ModesMode 0 (13

71 AT85C51SND3Bx7632A–MP3–03/06RegistersReset Value = 0000 0000bTable 81. TCON RegisterTCON (0.88h) – Timer/Counter Control Register7 6 5 4 3 2 1 0T

72AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 82. TMOD RegisterTMOD (0.89h) – Timer/Counter Mode Control Regi

73 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bTable 84. TL0 RegisterTL0 (0.8Ah) – Timer 0 L

74AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 87. SCHCLK RegisterSCHCLK (0.FEh) – Scheduler Clocks Register76543210- T0ETB2 T0ETB1 T0

75 AT85C51SND3Bx7632A–MP3–03/06Watchdog Timer The AT85C51SND3Bx implement a hardware Watchdog Timer (WDT) that automati-cally resets the chip if it i

76AT85C51SND3Bx 7632A–MP3–03/06Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST reg

77 AT85C51SND3Bx7632A–MP3–03/06RegistersReset Value = XXXX XXXXbReset Value = XXXX X000bTable 89. WDTRST RegisterWDTRST (0.A6h Write only) – Watchdo

78AT85C51SND3Bx 7632A–MP3–03/06Data Flow Controller The Data Flow Controller (DFC) embedded in the AT85C51SND3Bx is the multimedia data transfer mana

79 AT85C51SND3Bx7632A–MP3–03/06Table 92 shows the different peripherals (source or destination) ID number. These num-bers are used to program the SID

8AT85C51SND3Bx 7632A–MP3–03/06Table 3. Timer 0 and Timer 1 Signal DescriptionP4.6:0 I/OPort 4 P4 is a 7-bit bidirectional I/O port with internal pul

80AT85C51SND3Bx 7632A–MP3–03/06selected as source, the null device is always ready and sends the data (2 bytes) of the initialized CRC value MSB firs

81 AT85C51SND3Bx7632A–MP3–03/06Figure 46. Immediate Data Flow Abort DiagramFigure 47. Delayed Data Flow Abort DiagramData Flow Configuration Prior

82AT85C51SND3Bx 7632A–MP3–03/06RegistersReset Value = 0000 0000bTable 94. DFCON RegisterDFCON (1.89h) – DFC Control Register7 6 5 4 3 2 1 0- DFRES -

83 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000b3 DRDY0Channel 0 Destination Ready FlagSet by hardware when the source

84AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bReset Value = 0000 0000bTable 97. DFD0 RegisterDFD0 (1.8Ah) – DFC Cha

85 AT85C51SND3Bx7632A–MP3–03/06USB Controller The AT85C51SND3Bx Implements a USB controller allowing the AT85C51SND3Bx to act as a USB device or a US

86AT85C51SND3Bx 7632A–MP3–03/06Figure 50. USB ConnectionGeneral Operating ModesIntroduction After a hardware reset, the USB controller is disabled.

87 AT85C51SND3Bx7632A–MP3–03/06• The DPACC bit and the DPADD10:0 field can be set by software. The DPRAM is not cleared.• The SPDCONF bits can be set

88AT85C51SND3Bx 7632A–MP3–03/06There are 2 kinds of interrupts: processing (i.e. their generation are part of the normal processing) and exception (e

89 AT85C51SND3Bx7632A–MP3–03/06Speed ControlDevice Mode When the USB interface is configured in device mode, the speed selection (Full Speed or High

9 AT85C51SND3Bx7632A–MP3–03/06Clock Controller Table 4. Clock Signal DescriptionMemory Controllers Table 5. Secure Digital Card / MutiMediaCard Con

90AT85C51SND3Bx 7632A–MP3–03/06When using this mode, there is no influence over the USB controller.Memory Management The controller only supports the

91 AT85C51SND3Bx7632A–MP3–03/06• First, Pipe/Endpoint 0 to Pipe/Endpoint 5 are configured, in the growing order. The memory of each is reserved in th

92AT85C51SND3Bx 7632A–MP3–03/06OTG Timers Customizing It is possible to refine some OTG timers thanks to the OTGTCON register (see Table 108). This r

93 AT85C51SND3Bx7632A–MP3–03/06The control logic of the UVCC pad outputs 2 signals:• The “session_valid” signal is active high when the voltage on th

94AT85C51SND3Bx 7632A–MP3–03/06ID Detection The ID pin transition is detected thanks to the following architecture:Figure 58. ID Detection Input Blo

95 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0010 0000bReset Value = 0000 0000bReset Value = 0000 0000b0 VBUSTEVBUS Transition Interrupt Enable BitSe

96AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000bTable 105. UDPADDH RegisterUDPADDH (1.E4h) – USB Dual Port Ram Direct

97 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000bReset Value = 0000 0000b5 HNPREQHNP Request BitSet to initiate the HNP when the controller is

98AT85C51SND3Bx 7632A–MP3–03/06Reset Value = 0000 0000bTable 109. OTGIEN RegisterOTGIEN (1.E7h) – USB OTG Interrupt Enable Register7 6 5 4 3 2 1 0-

99 AT85C51SND3Bx7632A–MP3–03/06Reset Value = 0000 0000b3 ROLEEXIRole Exchange Interrupt FlagSet by hardware when the USB controller has successfully